Achieve low PLL jitter via improved power integrity (www.edn.com)

Best practices of PLL implementation

A PLL (phase locked loop) or frequency synthesizer is used to generate high frequency clocks to ADCs and other devices. It is crucial to maintain a very low jitter or phase noise in the PLL output to ensure high SNR (signal to noise ratio) in downstream devices, as governed by equation (1). Hence, it is very important for the designer to apply the following best practices during board level PLL implementation:

(i) ensure sufficient decoupling capacitor quantity for low switching noise from voltage supply to PLL

(ii) insert ferrite bead between analog and digital power net of PLL to prevent injection of digital transient noise to analog domain

(iii) generate PLL output in differential mode instead of single ended signal to minimize common mode noise

(iv) proper PCB layout routing for PLL signal (i.e., at least 30 mil away from other signals or parts) to minimize crosstalk

(v) use input reference frequency (i.e., crystal oscillator) with low noise

(vi) configure low pass filter in PLL with lower cut-off frequency to suppress the noise coupled into the phase detector, as shown in Figure 1

Figure 1. Basic block diagram of PLL

Effect of power integrity on jitter

A prototype PCB with PLL generating a 500MHz differential signal, powered by 3.3V from a DC-DC converter with 500kHz switching frequency, is implemented with application of points ii to vi above.

The jitter analysis of PLL signal in time domain is performed using EZJit test software in DSO80000 series oscilloscope (at least 3GHz bandwidth to cover 5th harmonic of the 500MHz signal) from Keysight. With reference to the analysis result shown in Figure 2, the PLL output has TJ (total jitter) of ~300ps or 15% of the 500MHz clock period, which is very high and unacceptable to the ADC.

Figure 2. PLL jitter for poor power integrity

In order to root out the noise spurs that couple into the PLL thru power net, probing of the signal in the frequency domain using a Keysight E4411B spectrum analyzer is performed. With reference to spectral analysis result shown in Figure 3, a noise spike of -49dBc at ~500kHz off center frequency of 500MHz is observed. This noise spike is coupled from the switching of the voltage regulator to PLL.

Figure 3. PLL spectrum for poor power integrity

The switching noise of voltage regulator is characterized in AC coupling mode of oscilloscope. The switching noise has very large amplitude of ~250mVpp or 7.5% of 3.3V by observing the oscilloscope waveform shown in Figure 4.

Figure 4. Noise ripple for poor power integrity

Based on the resonant frequency profile of different power network elements displayed in Figure 5, the switching frequency of 500kHz falls in the region of bulk bypass capacitors. In order to suppress the 500kHz switching noise, two low ESR 100µF capacitors are added in parallel to the power net near output pin of voltage regulator.

Figure 5. Resonance profile of PDN elements

Referring to the switching noise waveform in Figure 6, after adding more bulk bypass capacitors, the noise amplitude gets attenuated tremendously to ~50mVpp or 1.5% of 3.3V.

Figure 6. Noise ripple for improved power integrity

After observing a significant attenuation of switching noise in power net to PLL, its 500MHz output signal is characterized again in both time and frequency domain.

The spectral analysis result in Figure 7 indicates that the spike at 500kHz off the PLL output signal gets suppressed to -75dBc. Meanwhile, the jitter analysis result in Figure 8 indicates a tremendous reduction of TJ to 42ps or 2% of clock period of 500MHz.

Figure 7. PLL spectrum for improved power integrity

Figure 8. PLL jitter for improved power integrity

According to equation (2), noise in power net is generated when PDN impedance interacts with the transient current of all components connected to the power net (including voltage regulator and load ICs) over a wide band. By placing sufficient quantity of bypass and decoupling capacitors across the power net, PDN impedance is reduced and subsequently the power rail noise is attenuated. Ultimately, PLL output jitter is minimized.

Noise ripple = transient current x PDN impedance     (2)

Conclusion

It is essential that each of the best practices listed at the beginning of this article is applied in the implementation of PLLs on a PCB, especially the power integrity aspect. In the situation where power integrity simulation software is unavailable to be used, analytical and troubleshooting techniques discussed in the second section are applicable to root out the culprits of PLL jitter.

References

[1] “Power Distribution Network Planning“, by Barry Olney, In-Circuit Design Pty Ltd Australia

[2] “Basic Concepts of Power Distribution Network Design for High Speed Transmission“, by F.Carrio, V.Gonzalez and E.Sanchis

[3] “Fundamentals of Phase Locked Loops (PLLs)“, Analog Devices

[4] “ADC FUNDAMENTALS“, Analog Devices

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